As technology advances in the semiconductor field, devices such as processors incorporate ever-increasing amounts of circuitry. Over time, processor designs have evolved from a collection of independent integrated circuits (ICs), to a single integrated circuit, to multicore processors that include multiple processor cores within a single IC package. As time goes on, ever greater numbers of cores and related circuitry are being incorporated into processors and other semiconductors.
Multicore processors are being extended to include additional functionality by incorporation of other functional units within the processor. For example with smaller form factor systems, there is a push towards integrating several discrete platform components within the same package. As such, components are combined either on the same physical die or within a shared common socket. Power and thermal specifications are typically defined for a socket. On legacy platforms where such components are distinct physical chips on the platform, their power and thermal design points are individually specified. With integration of a package, a common power and thermal specification is shared by multiple die.
Thermal design power (TDP) is one such constraint that is specified for an integrated package. TDP defines the steady state power that the package can consume and still remain within the cooling capacity of the platform. When TDP is specified for the entire package, it leads to the question of how the power envelope is to be shared between different compute entities. Statically assuming worst case power consumption on each sub-component of a package can lead to taking large guard bands. As a result, operation of the compute entities is at a lower than optimal frequency, and thereby leaves power and performance unavailable.